The asic handbook

The book begins with a detailed overview of the main phases of an ASIC-based development project, then walks through every step of the process, presenting best-practices methodologies proven to succeed. Nigel Horspool and Peter Gorman introduce detailed techniques for designing for reuse, improving the quality of initial designs and architectures, more effective VHDL/Verilog coding, system simulation, synthesis, DFT, design verification, and more. The book also contains detailed coverage of management and leadership issues, including team building, planning, risk reduction, and ASIC vendor management.

For every manager and team member involved with ASIC development, including ASIC design engineers, ASIC project leaders and ASIC design team managers.

Table of Contents

Preface ..... xv

Acknowledgments ..... xix

Chapter 1: Phases of an ASIC Project ..... 1

1.1: Introduction ..... 1

1.2: List of Phases ..... 1

1.3: Prestudy Phase ..... 3

1.4: Top-Level Design Phase ..... 5

1.5: Module Specification Phase ..... 8

1.6: Module Design ..... 11

1.7: Subsystem Simulation ..... 15

1.8: System Simulation/Synthesis ..... 17

1.9: Layout and the Backend Phase ..... 23

1.10: Postlayout Simulation/Synthesis ..... 25

1.11: ASIC Sign-Off ..... 27

1.12: Preparation for Testing Silicon ..... 28

1.13: Testing of Silicon ..... 30

1.14: Summary ..... 33

Chapter 2: Design Reuse and System-on-a-Chip Designs ..... 35

2.1: Introduction ..... 35

2.2: Reuse Documentation ..... 36

2.3: Tips and Guidelines for Reuse ..... 39

2.4: SoC and Third-Party IP Integration ..... 44

2.5: System-Level Design Languages ..... 51

2.6: Virtual Socket Interface Alliance ..... 51

2.7: Summary ..... 51

Chapter 3: A Quality Design Approach ..... 53

3.1: Introduction ..... 53

3.2: Project Design Documentation ..... 54

3.3: Reviews ..... 57

3.4: Module Design and Reviewing ..... 58

3.5: Quality System Simulations ..... 64

3.6: Review Checklists ..... 64

3.7: Summary ..... 66

Chapter 4: Tips and Guidelines ..... 69

4.1: Introduction ..... 69

4.2: General Coding Guidelines ..... 69

4.3: Coding for Synthesis ..... 78

4.4: Coding for Testability ..... 83

4.5: Coding for Multiple Clock Domains ..... 87

4.6: Summary ..... 92

Chapter 5: ASIC Simulation and Testbenches ..... 93

5.1: Introduction ..... 93

5.2: Quality Testbenches ..... 94

5.3: Simulation Strategy ..... 101

5.4: Extending the Simulation Strategy ..... 105

5.5: Reducing Top-Level Simulation Run Times ..... 106

5.6: Speeding Up Debugging ..... 108

5.7: Different Types of Testing ..... 109

5.8: Generation of ASIC Test Vectors ..... 112

5.9: Summary ..... 113

Chapter 6: Synthesis ..... 115

6.1: Introduction ..... 115

6.2: The General Principle ..... 116

6.3: Top-Down versus Bottom-Up Synthesis ..... 116

6.4: Physical Synthesis Tools ..... 117

6.5: Scripts versus GUIs ..... 118

6.6: Common Steps in Synthesis Scripts ..... 119

6.7: Directory Structures ..... 129

6.8: Special Cells ..... 129

6.9: Miscellaneous Synthesis Terms, Concepts and Issues ..... 130

6.10: Managing Multiple Clock Domains ..... 135

6.11: Managing Late Changes to the Netlist ..... 136

6.12: Summary ..... 138

Chapter 7: Quality Framework ..... 139

7.1: Introduction ..... 139

7.2: The Directory Structure ..... 139

7.3: Documentation Storage ..... 143

7.4: Freezing Documents and Controlled Updates ..... 143

7.5: Fault Report Database ..... 143

7.6: Source Code Control ..... 144

7.7: Makefiles/Simulation Scripts ..... 144

7.8: Company-Defined Procedures ..... 144

7.9: Summary ..... 145

Chapter 8: Planning and Tracking ASIC Projects ..... 147

8.1: Overview ..... 147

8.2: Basic Planning Concepts ..... 147

8.3: Process for Creating a Plan ..... 150

8.4: Tracking ..... 157

8.5: Summary ..... 159

Chapter 9: Reducing Project Risks ..... 161

9.1: Introduction ..... 161

9.2: Trade-Offs Between Functionality, Performance, Cost and Timescales ..... 162

9.3: Minimizing Development Risks ..... 163

9.4: Reducing the Risk of Design Bugs ..... 168

9.5: Risks in Meeting ASIC Vendor Criteria ..... 173

9.6: Summary ..... 174

Chapter 10: Dealing with the ASIC Vendor ..... 177

10.1: Introduction ..... 177

10.2: Using the Vendor's Expertise ..... 177

10.3: Vendor Selection ..... 178

10.4: ASIC Vendor Services ..... 183

10.5: Effect of the Vendor on Timescales ..... 184

10.6: Summary ..... 188

Chapter 11: Motivation and People Management ..... 189

11.1: Introduction ..... 189

11.2: Managing Engineers with Different Experience Levels ..... 189

11.3: Maslow's Hierarchy of Needs ..... 191

11.4: Getting to Know the Team ..... 193

11.5: Goal Setting ..... 195

11.6: Communicating Project Information ..... 196

11.7: Training ..... 198

11.8: Summary ..... 199

Chapter 12: The Team ..... 201

12.1: Introduction ..... 201

12.2: The Project Leader/Project Manager ..... 202

12.3: The Wider Team ..... 203

12.4: Key Roles Within the Team ..... 204

12.5: Summary ..... 207

Chapter 13: Project Manager Skills ..... 209

13.1: Introduction ..... 209

13.2: Running Meetings ..... 209

13.3: Interviewing ..... 210

13.4: Time Management ..... 212

13.5: Summary ..... 213

Chapter 14: Design Tools ..... 215

14.1: Introduction ..... 215

14.2: Hierarchy Tools ..... 216

14.3: Input Tools ..... 216

14.4: Code Analysis Tools ..... 217

14.5: Revision Management Tools ..... 217

14.6: Testbench and Validation Tools ..... 217

14.7: Synthesis Tools ..... 221

14.8: Static-Timing Analyzers ..... 222

14.9: Summary ..... 222

Bibliography ..... 223

About the Authors ..... 225

Index ..... 227