Modeling, Synthesis, and Rapid Prototyping with The Verilog HDL
723 pages, parution le 01/06/2000
Résumé
Designed for advanced undergraduate and graduate computer
science, computer engineering and electrical engineering
courses in digital design and hardware description
languages, this textbook presents an integrated treatment
of the Verilog hardware description language (HDL) and its
use in VLSI, circuit modeling/design, synthesis, and rapid
prototyping. This product is a selection from the Xilinx
Design Series.
2. Hardware Modeling with the Verilog HDL.
3. Event-Driven Simulation and Testbenches.
4. Logic System, Data Types, and Operators for Modeling in Verilog HDL.
5. User-Defined Primitives.
6. Verilog Models of Propagation Delay.
7. Behavioral Descriptions in Verilog HDL.
8. Synthesis of Combinational Logic.
9. Synthesis of Sequential Logic.
10. Synthesis of Language Constructs.
11. Switch-Level Models in Verilog.
12. Design Examples in Verilog.
13. Rapid Prototyping with Xilinx FPGAs.
Appendixes.
Are you looking for an undergraduate text that treats the use of Verilog in synthesis? Are you looking for a text that describes both the language and its use with modern circuit synthesis?
Features
- Shows the use of Verilog HDL in digital design and synthesis using examples (e.g., FIFO-based data acquisition system design, microcontroller design, electronic game design, and client-server polling circuit design). Source code files for examples are included. Examples are encapsulated complete, and the source code has been tested.
- Illustrates descriptive styles that synthesize and identifies pitfalls that either prevent synthesis or lead to unexpected and undesirable results.
- Includes results of simulation and synthesis.
- Over 200 complete and carefully chosen examples.
- Special Feature: “Xilinx® Student Software (Foundations Series Express 1.5" and the SILOS Verilog circuit simulator (demonstration version) are packaged with the book providing a complete learning environment.
-
- Includes discount coupon to purchase optional FPGA hardware.
- Problems and design exercises at the end of chapters.
-
- Includes ASIC cell library.
1. Introduction to Electronic Design
Automation.
Electronic Design
Automation. A Brief History of HDLs. The Role and
Requirements of HDLs in EDA. Benefits of Using HDLs in EDA.
Summary. Problems.
2. Hardware Modeling with the Verilog HDL.
Hardware Encapsulation:
the Verilog Module. Hardware Modeling: Verilog Primitives.
Descriptive Styles. Structural Connections. Behavioral
Descriptions in Verilog. Hierarchical Descriptions of
Hardware. Structured (Top-Down) Design Methodology. Arrays
of Instances. Using Verilog for Synthesis. Language
Conventions. Representation of Numbers. Summary.
Problems
3. Event-Driven Simulation and Testbenches.
Simulation with Verilog.
Design Unit Testbench. Summary. Problems.
4. Logic System, Data Types, and Operators for Modeling in Verilog HDL.
Variables. Logic Value
Set. Data Types. Strings. Constants. Operators. Expressions
and Operands. Operator Precedence. Summary. Problems.
5. User-Defined Primitives.
UDP: Combinational
Behavior. UDP: Sequential Behavior. Initialization of
Sequential Primitives. Summary. Problems
6. Verilog Models of Propagation Delay.
Built-In Constructs for
Delay. Signal Transitions. Verilog Models for Gate
Propagation Delay (Inertial Delay). Time Scales for
Simulation. Verilog Models for Net Delay (Transport Delay).
Module Paths and Delays. Paths Delays and Simulation.
Inertial Delay Effects and Pulse Rejection. Summary.
Problems.
7. Behavioral Descriptions in Verilog HDL.
Verilog Behaviors.
Behavioral Statements. Procedural Assignment. Procedural
Continuous Assignment. Procedural Timing Controls and
Synchronization. Intra-Assignment Delay—Blocked
Assignments. Non-blocking Assignment. Intra-Assignment
Delay—Non-Blocking Assignment. Simulation of
Simultaneous Procedural Assignment. Constructs for Activity
Flow Control. Repeated Intra-Assignment Delay.
Indeterminate Assignments and Ambiguity. Constructs for
Activity Flow Control. Tasks and Functions. Summary of
Delay Constructs in Verilog. System Tasks for Timing
Checks. Variable Scope Revisited. Module Contents.
Behavioral Models of Finite State Machines. Summary.
Problems.
8. Synthesis of Combinational Logic.
HDL-Based Synthesis.
Technology-Independent Design. Benefits of Synthesis.
Synthesis Methodology. Vendor Support. Styles for Synthesis
of Combinational Logic. Technology Mapping and Shared
Resources. Three-State Buffers. Three-State Outputs and
Don't Cares. Summary. Problems.
9. Synthesis of Sequential Logic.
Synthesis of Sequential
UDPs. Synthesis of Latches. Synthesis of Edge-Triggered
Flip-Flops. Registered Combinational Logic. Shift Registers
and Counters. Synthesis of Finite State Machines. Resets.
Synthesis of Gated Clocks. Design Partitions and
Hierarchical Structures. Summary. Problems.
10. Synthesis of Language Constructs.
Synthesis of Nets.
Synthesis of Register Variables. Restrictions on Synthesis
of "x" and "z". Synthesis of Expressions and Operators.
Synthesis of Assignments. Synthesis of case and Conditional
(if...) Statements. Synthesis of Resets. Timing Controls in
Synthesis. Synthesis of Multi-Cycle Operations. Synthesis
of Loops. Synthesis of fork...join Blocks. Synthesis
of the disable Statement. Synthesis of User-Defined
Tasks. Synthesis of User-Defined Functions. Synthesis of
Specify Blocks. Synthesis of Compiler Directives. Summary.
Problems.
11. Switch-Level Models in Verilog.
MOS Transistor Technology.
Switch-Level Models of MOS Transistors. Switch-Level Models
of Static CMOS Circuits. Alternative Loads and Pull Gates.
CMOS Transmission Gates. Bi-Directional Gates (Switches).
Signal Strengths. Ambiguous Signals. Strength Reduction by
Primitives. Combination and Resolution of Signal Strengths.
Signal Strengths and Wired Logic. Summary. Problems.
12. Design Examples in Verilog.
FIFO—Buffers for
Data Acquisition. FIFO Application: Temperature Monitor
System. UART. Bit-Slice Microcontroller. Summary.
Problems.
13. Rapid Prototyping with Xilinx FPGAs.
Introduction to FPGAs.
Role of FPGAs in the ASIC market. FPGA Technologies. The
Xilinx SC3000 FPGA Family. The Xilinx XC4000 FPGA Family.
Rapid Prototyping with Verilog and FPGAs. Design Exercises.
Summary. Problems.
Appendixes.
Predefined Primitives.
Verilog Keywords. Verilog Operators and Precedence.
Backus-Naur (BNF) Formal Syntax Notation. System Tasks and
Functions. Verilog Language Formal Syntax. Programming
Language Interface (PLI). Compiler Directives. Flip-Flop
and Latch Types.
Caractéristiques techniques
| PAPIER | |
| Éditeur(s) | Prentice Hall |
| Auteur(s) | Michael D. Ciletti |
| Parution | 01/06/2000 |
| Nb. de pages | 723 |
| Format | 18 x 24 |
| Couverture | Relié |
| Poids | 1277g |
| Intérieur | Noir et Blanc |
| EAN13 | 9780139773983 |
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