InfiniBand Network Architecture
PC System Architecture Series
Résumé
InfiniBand is a new networking specification that revolutionizes the interconnect between processor and IO subsystems in the datacenter environment. InfiniBand delivers better performance, flexibility, and scalability than alternative bus network architectures. Copper wire and fiber optic InfiniBand links offer data rates ranging from 2.5 Gb/s to 30 Gb/s. This technology easily surpasses the performance of competing network infrastructures by providing kernel bypass and memory-to-memory transfer capabilities.
InfiniBand Network Architecture is a comprehensive guide to InfiniBand technology. It describes all hardware and software operational aspects of InfiniBand networking. Using the same building-block approach found in all of the books in the PC System Architecture Series, this book details important concepts relating to the design and implementation of data networks using this emerging standard. A broad overview of the InfiniBand specification is provided, as well as detailed descriptions of all of the architecture's operational characteristics.
Specific topics of interest include:
- Packet addressing, channel adapters, and the role of switches, routers, and repeaters
- Queue Pair (QP) creation and operation
- Transfer types, including connected, datagram, and raw datagram service
- Send/receive operations, such as Send, RDMA Read and Write, and atomic Read/Modify/Write (RMW) operations
- Link and physical layer descriptions
- Subnet-local and global addressing
- The Subnet Manager (SM) and the Subnet Administrator (SA)
- Performance, communication, device,and baseboard managers
Contents
- 1. About This Book.
-
I. INTRODUCTORY TOPICS.
- 2. Basic Terms and Concepts.
- 3. Intro to Attributes and Managers.
- 4. QP: Message Transfer Mechanism.
- 5. Intro to Transport Types.
- 6. Intro to Send/Receive Operations.
- 7. Division of Labor.
- 8. Subnet-Local Addressing.
- 9. Global Addressing.
- 10. Intro to the Managers.
- 11. Intro to Connection Establishment.
- 12. PSN Usage.
-
II. QP CREATION AND OPERATION.
- 13. QP Verbs and QP State Machine.
- 14. WRs, WQEs, and CQEs.
- 15. Asynchronous Events and Errors.
-
III. PROTECTION MECHANISMS.
- 16. Memory Protection.
- 17. Other Protection Mechanisms.
-
IV. DETAILED DESCRIPTION OF THE TRANSPORT SERVICES.
- 18. RC Transport Service.
- 19. UC Transport Service.
- 20. RD Transport Service.
- 21. UD Transport Service.
- 22. Raw Transport Service Types.
- 23. Multicasting.
- 24. Automatic Path Migration.
- 25. Static Rate Control.
-
V. LINK AND PHYSICAL LAYER DESCRIPTIONS.
- 26. Detailed Description of Link Layer.
- 27. Detailed Physical Layer Description.
-
VI. THE SM AND SA 759.
- 28. The SMI.
- 29. Detailed Description of MADs.
- 30. SM Methods and Attributes.
- 31. Multiple SMs.
- 32. Discovery.
- 33. The GSI.
- 34. Detailed Description of SA.
-
VII. GENERAL SERVICES.
- 35. Baseboard Management.
- 36. Performance Management.
- 37. Communications Management.
- 38. Device Management.
L'auteur - Tom Shanley
is one of the world's foremost authorities on PC system architecture and has personally trained thousands of engineers in hardware and software design.
Caractéristiques techniques
PAPIER | |
Éditeur(s) | Addison Wesley |
Auteur(s) | Tom Shanley |
Parution | 26/11/2002 |
Nb. de pages | 1276 |
Format | 18,5 x 23,5 |
Couverture | Broché |
Poids | 1875g |
Intérieur | Noir et Blanc |
EAN13 | 9780321117656 |
ISBN13 | 978-0-321-11765-6 |
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