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High performance memory systems
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High performance memory systems

High performance memory systems

Collectif Springer

310 pages, parution le 09/12/2003

Résumé

The more rapid rate of increase in the speed of microprocessor technology than in memory speeds has created a serious 'memory gap' for computer designers and manufacturers. "High Performance Memory Systems" addresses this issue and examines all aspects of improving the memory system performance of general-purpose programs. Current research highlights from both industry and academia focus on: coherence, synchronization, and allocation; power-awareness, reliability, and reconfigurability; software-based memory tuning; architecture design issues; and workload considerations.

Topics and features:

  • both harware and software approaches to scalability and speed disparities are considered *introductory chapter provides broad examination of high performance memory systems
  • includes coverage of topics from several important international conferences

Edited by leading international authorities in the field, this new work provides a survey from researchers and practitioners on advances in technology, architecture, and algorithms that address scalability needs in multiprocessors and the expanding gap between CPU/network and memory speeds. It is ideally suited to researchers and R & D professionals with interests or practice in computer engineering, computer architecture, and processor architecture.

Contributors : Hadimioglu, H.; Kaeli, D.; Kuskin, J.; Nanda, A.; Torrellas, J. (Eds.) and about 50 authors.

Contents

  • Introduction to high-performance memory systems
  • Coherence, synchronization, and allocation
    • Speculative locks : concurrent execution of critical sections in shared-memory multiprocessors
    • Dynamic verification of cache coherence protocols
    • Timestamp-based selective cache allocation
  • Power-aware, reliable, and reconfigurable memory
    • Power-efficient cache coherence
    • Improving power efficiency with an asymmetric set-asociative cache
    • Memory issues in hardware-supported software safety
    • Reconfigurable memeory module in the RAMP system for stream processing
  • Software-based memory tuning
    • Performance of memory expansion technology (MXT)
    • Profile-tuned heap access
    • Array merging : A technique for improving cache and TLB behavior
    • Software logging under speculative parallelization
  • Architecture-based memory tuning
    • An analysis of scalar memory accesses in embedded and multimedia systems
    • Bandwidth-based prefetching for constant-stride arrays
    • Performance potential of effective address prediction of load instructions
  • Workload considerations
    • Evaluating novel memory system alternatives for speculative multithreaded computer systems
    • Evaluation of large L3 caches using TPC-H trace samples
    • Exploiting intelligent memory for database workloads
  • Index

L'auteur - Collectif Springer

Autres livres de Collectif Springer

Caractéristiques techniques

  PAPIER
Éditeur(s) Springer
Auteur(s) Collectif Springer
Parution 09/12/2003
Nb. de pages 310
Format 16 x 24
Couverture Relié
Poids 585g
Intérieur Noir et Blanc
EAN13 9780387003108
ISBN13 978-0-387-00310-8

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